Area-Universal Circuits with Constant Slowdown

نویسندگان

  • Sandeep N. Bhatt
  • Gianfranco Bilardi
  • Geppino Pucci
چکیده

An area-universal VLSI circuit can be programmed to emulate every circuit of a given area, but at the cost of lower area-time performance. In particular, if a circuit with area-time bounds (A; T ) is emulated with a universal circuit with bounds (Au; Tu); we say that the universal circuit has blowup Au=A and slowdown Tu=T . A central question in VLSI theory is to investigate the inherent costs and tradeoffs of universal circuit designs. Prior to this paper, universal designs with O(1) blowup and O(logA) slowdown for areaA circuits were known. Universal designs for area-A circuits of O(pA1+ logA) nodes, with O(A ) blowup and O(log logA) slowdown, had also been developed. However, the existence of universal circuits with O(1) slowdown and relatively small blowup was an open question. In this paper, we settle this question by designing an area-universal circuit U A with O (1= ) slowdown and O 2A log4A blowup, for any value of the parameter , 1= logA 1. By varying , we obtain universal circuits which operate at different points in the spectrum of the slowdownblowup tradeoff. In particular, when is chosen to be a constant, our universal circuit yields O(1) slowdown.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Area-time tradeoffs for universal VLSI circuits

An area-universal VLSI circuit can be programmed to emulate every circuit of a given area, but at the cost of lower area-time performance. In particular, if a circuit with area-time bounds (A, T ) is emulated by a universal circuit with bounds (Au, Tu), we say that the universal circuit has blowup Au/A and slowdown Tu/T . A central question in VLSI theory is to investigate the inherent costs an...

متن کامل

Universal Emulations with Sublogarithmic Slowdown

The existence of bounded degree networks which can emulate the computation of any bounded degree network of the same size with logarithmic slowdown is well-known. The butterfly is an example of such a universal network. Leiserson was the first to introduce the concept of an area-universal network: a network with VLSI layout area A which can emulate any network of the same size and layout area w...

متن کامل

Towards Practical Universal Search

Universal Search is an asymptotically optimal way of searching the space of programs computing solution candidates for quickly verifiable problems. Despite the algorithm’s simplicity and remarkable theoretical properties, a potentially huge constant slowdown factor has kept it from being used much in practice. Here we greatly bias the search with domain-knowledge, essentially by assigning short...

متن کامل

Deterministic On-Line Routing on Area-Universal Networks (Extended Abstract)

We present two deterministic routing networks, the pruned butterfly and the sorting fat-tree. Both networks are area-universal, i.e., they can simulate any other routing network fitting in similar area with polylogarithmic slowdown. Previous area-universal networks were either for the off-line problem, where the message set to be routed is known in advance and substantial precomputation is perm...

متن کامل

Computing Static Slowdown Factors under EDF Scheduling when Deadline less than Period

Slowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic Voltage Scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings. This paper describes computation of slowdown factor for a task set with an underlying dynamic priority scheduler such as Earliest Deadline First (EDF) ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1999